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Altera_Forum
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9 years ago

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_Forum's avatar
Altera_Forum
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9 years ago

My colleague Adrian Byszuk has found the incompatibility of my bridge with the AXI4 specification.

According to thre AXI4 specification: http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/axi4_specification.pdf page A3-36 & A3-37, "On master and slave interfaces there must be no combinatorial paths between input and output signals."

Current implementation boosts performance by violating that requirement.

At the moment i'm not sure if that incompatibility justifies the behaviour of the Qsys interconnect.