Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMy AXI4 Lite slave hangs CPU after read. Write transactions work correctly
Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Could you put an SR in on this? I had a discussion with them just recently about the Qsys interconnect components, and bad behavior, and I think they are only recently really debugging AXI. I could be wrong, but anything to get a more robust Qsys -> AXI interconnect is good in my book. --- Quote End --- OK. I have created Altera SR#: 11234425: Qsys interconnect incorrectly incorrectly handles AXI4-Lite read transactions (New Service Request)
