My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

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Could you put an SR in on this? I had a discussion with them just recently about the Qsys interconnect components, and bad behavior, and I think they are only recently really debugging AXI. I could be wrong, but anything to get a more robust Qsys -> AXI interconnect is good in my book.

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OK. I have created Altera SR#: 11234425: Qsys interconnect incorrectly incorrectly handles AXI4-Lite read transactions (New Service Request)