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Altera_Forum
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10 years ago

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_Forum's avatar
Altera_Forum
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10 years ago

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In that version of the project there was only standard sysid_qsys block connected as an "Avalon Memory Mapped Slave" and my axi2ipb bridge.

With best regards,

Wojtek

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Could you put an SR in on this? I had a discussion with them just recently about the Qsys interconnect components, and bad behavior, and I think they are only recently really debugging AXI. I could be wrong, but anything to get a more robust Qsys -> AXI interconnect is good in my book.