My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

--- Quote Start ---

In that version of the project there was only standard sysid_qsys block connected as an "Avalon Memory Mapped Slave" and my axi2ipb bridge.

With best regards,

Wojtek

--- Quote End ---

Could you put an SR in on this? I had a discussion with them just recently about the Qsys interconnect components, and bad behavior, and I think they are only recently really debugging AXI. I could be wrong, but anything to get a more robust Qsys -> AXI interconnect is good in my book.