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Altera_Forum
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9 years ago

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Do you have any other devices in the interconnect, such as an AXI bridge?

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In that version of the project there was only standard sysid_qsys block connected as an "Avalon Memory Mapped Slave" and my axi2ipb bridge.

With best regards,

Wojtek