My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

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OK. So the problem was caused by the strange behavior (bug?!) of the qsys interconnect, which during the read transaction kept the rready asserted in that cycle, in which it received arready, but it was apparently not able to accept rvalid . As my slave (and bridge) produced RDATA in the same cycle, the bridge asserter RVALID and assumed transaction to be finished. It seems that Qsys Interconnect ignored the RVALID='1' in that cycle and waited for it starting from the next cycle, causing the bus to lock.

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Do you have any other devices in the interconnect, such as an AXI bridge?