Multiprocessor Nios 2 System + VIC (urgent!)

Now, I'm spending over two weeks on VIC and it doesn't work as expected.

This is a serious problem for me, my bachelor thesis will end in less than 4 weeks.

I read all threads, containing "vic" or "vector interrupt controller" in this forum. I read a lot of altera literature:

- AN595: Vectored Interrupt Controller Usage and Applications

- 8. Exception Handling

- Creating Multiprocessor Nios II Systems

- Nios II Embedded Design Suite Release Notes and Errata

- Instantiating the Nios II Processor in SOPC Builder

Inspected the AN595 and nios ii multiprocessor design example (http://www.altera.com.cn/support/examples/nios2/exm-multi-nios2-hardware.html) examples and it is still not working. Where is the mistake ?

software environment: Quartus II and Nios II IDE SBT v9.1sp2

system environment: 3 CPUs, shared memory data exchange

sopc-overview (http://img801.imageshack.us/img801/8787/pic1i.png)

sopc-overview (http://img576.imageshack.us/img576/6202/pic2pd.png)

sopc-nios ii -> advanced features (http://img256.imageshack.us/img256/8326/pic3y.png)

sopc-inthand (http://img841.imageshack.us/img841/9891/pic4a.png)

use-case: cpu1 writes in cpu1_IntGen pio which is connected with cpu2_IntHand pio. cpu2_IntHand triggers on rising and falling edges, creating an interrupt request. This is done 10x times, with 50 ms delay.

I tested this use case on systems without a vector interrupt controller. All fine!

(One project each for cpu1 and cpu2. Then "Debug As" both projects)

code:

cpu1

void task1(void* pdata)
{
  int i;
  for(i=0; i<5; i++) {
	  IOWR(PIO_PIN_OUT_BASE, 0, 0xff);
	  IOWR_ALTERA_AVALON_PIO_DATA(CPU1_INTGEN_BASE, 0x1);
	  OSTimeDlyHMSM(0, 0, 0, 50);
	  IOWR(PIO_PIN_OUT_BASE, 0, 0xff);
	  IOWR_ALTERA_AVALON_PIO_DATA(CPU1_INTGEN_BASE, 0x0);
	  OSTimeDlyHMSM(0, 0, 0, 50);
  }
  printf("Sender finished");
}

cpu2

int main()
{
  printf("Starting internal interrupt roundtrip performance test.\n");
  interrupt_watch_value = 0;
  timer_interrupt_latency_init ((void *)CPU2_INTHAND_BASE,CPU2_INTHAND_IRQ_INTERRUPT_CONTROLLER_ID,CPU2_INTHAND_IRQ);
  printf("%d\n", &timer_interrupt_latency_irq);
  while (interrupt_watch_value < 10) {
  /* wait for interrupt */
  }
  printf("Interrupt occured");
  printf("\nSending EOT to force an exit.%c",EOT);
  return 0;
}
// ISR INIT
void timer_interrupt_latency_init (void* base, alt_u32 irq_controller_id, alt_u32 irq)
{
  /* Register the interrupt */
  alt_ic_isr_register(irq_controller_id, irq, timer_interrupt_latency_irq, base, NULL);
  /* Enable CPU2 interrupts (PIN1) */
  IOWR_ALTERA_AVALON_PIO_IRQ_MASK(CPU2_INTHAND_BASE, 0x2);
  /* Reset the edge capture register. */
  IOWR_ALTERA_AVALON_PIO_EDGE_CAP(CPU2_INTHAND_BASE, 0x2);
}
// ISR
void timer_interrupt_latency_irq (void* base)
{
  IOWR(PIO_PIN_OUT_BASE, 0, 0x0); //set to low, stop DigiView timing analyzing
  IOWR_ALTERA_AVALON_PIO_EDGE_CAP(CPU2_INTHAND_BASE, 0x2);
  /*Stop timer */
  interrupt_watch_value += 1;
}

problem: In debug mode, there is no output when more than one cpu is used (simple texts with printf). Alone, when only one cpu is used, all fine !

Even sometimes, an interrupt request is processed, but only once. Why ?

I appreciate any comment, thanks.

Regards,

R2-D2