Multiprocessor configuration

I'm about to start work on adding a second processor to my design. The plan is to have the second processor work autonomously in relation to the current processor -- the only data sharing will be instruction and data space. No other peripherals will be shared and there will be no communications between the processors.

My current configuration contains a single NIOS II/f connected to a FLASH via a tristate bridge and SRAM via a tristate bridge. If I am understanding the multiprocessor tutorial well enough, all I need to do is connect the second processor to the same bridges and make sure to maintain separate memory partitions between the two (ie. no overlapping of physical memory space). The generated memory fabric should take care of arbitrating access between the cpus and the memory. I'll additionally need to assign one of the devices as the FLASH master and disable the FLASH initialization in the second CPU.

Is this correct? Am I missing anything? It just seems too simple. :)

One area I'm uncertain of is the configuration of the bridges. The tutorial has them sharing data & address signals under the "Shared Signals" configuration. If I set my configuration in a similar manner, can I truly rely on the fabric to take care of preventing data & instruction SRAM accesses by each CPU from stepping on each other? Once again, it just seems too simple -- I feel like I need to configure *more* *stuff* to prevent problems from occurring. :)

Thanks!

--tim