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Altera_Forum
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15 years ago

Multiple NiosII System

Hello everybody! It's my first post on this forum so a quick presentation to start : I'm a french student in the engineering school Polytech'Paris UPMC and I'm actually working on FPGA for a ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The Avalon bus will arbitrate between the 2 cpus' (or any other master's) accesses to flash, the only issue with flash will be erases and writes.

Intercommunication is probably best done through uncached accesses to an internal memory area (possibly tightly-coupled to both cpus). If you need a larger shared buffer (in external memory) then take care to flush/invalidate the caches and use the internal memory for synchronisation (etc).

For synchronisation look upo Dekker's algorithm.