Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Multiple NiosII System

Hello everybody! It's my first post on this forum so a quick presentation to start : I'm a french student in the engineering school Polytech'Paris UPMC and I'm actually working on FPGA for a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi!

Thank you for your answers!

Concerning Sheldon you're right it's really similar ^^. I don't know where this idea come from, it was suggested by our school but I think that the idea come from the San Diego State University because we are working in partnership with them.

Concerning my question, I understand what you suggest dsl. It certainly could be a solution.

I'm thinking to another thing. Is it possible to share the Flash memory between the two CPU, and to lock one CPU in reset until the first finish reading the content of the flash. Next, when the first CPU is running and don't need more access to the flash, it unlock the second which can read from the flash without conflict. Could this be a solution?

The problem with sharing the flash memory is that no mechanism enable the user to secure the access because the two CPUs are independent, but if the CPUs are not reading from the flash at the same time, it can work no?

I don't know if I forget something...

Thank you,

Nicolas