Can anybody point me to information regarding multiple (2 to 4) NIOS II cores? We are using the Stratix development board (as a reference design) and I wondered how much flexibility we had in hardware and software. Any help is appreciated.

It shouldn&#39;t be too much different then NIOS I (somewhere there is a document for NIOS I that gives a tutorial of how to do multiple cores in one SOPC). When/if you download the code over JTAG you need to tell it what you plan on targetting. If you have 2 CPUs. Try memory for each core. Then once you get the hang of it you might be able to use the same code memory (if they run the same software that is). What are you trying to do by the way?

I have a design and some info I have sent to others. Nios II is much easier to do multi cpu than Nios I. email me off line khallbec@altera.com

Really? How so? (I thought NIOS I was pretty easy to do this with using shared memory).

OK, here&#39;s some instructions (nios II). I&#39;m looking for the info on the differences btw NI and NII. Kerri ** I started with a standard_1s40 design (I used the verilog version, but it doesn&#39;t matter). In SOPC Builder Open SOPC Builder. Add (another) Nios II Processor I chose small, software breakpoints only. choose any variant; doesn&#39;t matter. Rename cpu_0 to "second_cpu". note that "second_cpu" comes up showing the masters connection columns, and that the masters are not connected to any devices. Change second_cpu jtag_debug_module base address to "0x00930000". (by default, it will come up with base address 0x0. this will conflict with ext_flash when we connect the data master to ext_flash). Add a jtag_uart instance. Rename "jtag_uart_0" to "second_jtag_uart" Change jtag_uart_0 base address to 0x00940000. (not necessary, but sopc builder assigned it a weird base address when i added it). Connected the second_cpu instruction master to ext_ram_bus, onchip_ram_64_kbytes, sdram (* connect to some memory device) Connected the second_cpu data master to ext_ram_bus. onchip_ram_64_kbytes, led_pio, lcd_display, seven_seg_pio, button_pio, second_jtag_uart, and sdram. (i connected to so much stuff because i wanted to run "count_binary" on it.) Changed the IRQ for button_pio from "NC" to "2" for second_cpu. (needed for count_binary) Changed the IRQ for second_jtag_uart from "NC" to "5" for second_cpu. (needed for any jtag_uart stuff using HAL) Kept the IRQ for lan91c111 as "NC" (default). (* connect to some memory device) I disconnected second_jtag_uart from cpu&#39;s data master (remains connected to second_cpu&#39;s data master) Go to More "second_cpu" Settings tab. Change Reset Address to onchip_ram_64_kbytes. TRICKY: Change Exception Address Offset to 0x00800020. You SHOULD change the exception address, because N2IDE will use the exception address as the basis for where to build software for the CPU. if you do not change the exception address, you may inadvertently cause both CPUs to be running the same software, or even worse, writing over the same area with one CPU while another is running in it! You&#39;re finished. Hit the Generate button. Notes on SOPC Generation For generation of the cpu that exists in the design, you&#39;ll get this warning in the file cpu_gen_log_0.txt: Warning: currently assigned JTAG instance ID 0 for cpu/jtag_debug_module is shared by second_cpu/jtag_debug_module. Reassigned to 1. This is perfectly fine, and no cause to worry. It just means that you&#39;ll have to recompile any software associated with this cpu. You&#39;d be wise to do so after SOPC generation anyway. This design took about 7.5 minutes to generate on my system. In Quartus 1 Compile! This can be done simultaneously with Nios II IDE Compilation, below. Nios II IDE, Compilation Open Nios II IDE. I did so by clicking on the "Run Nios II IDE" button in SOPC Builder after system generation was complete. File -> New -> Project..., Altera Nios II , C/C++ Application, click "Next >" Select Project Template to Hello World. Reassign Name: to "cpu_hello_world". Defaults to correctly selected SOPC Builder System and CPU "cpu", so I didn&#39;t have to change it. Press "Finish" (accept default of making a new system library for this). File -> New -> Project..., Altera Nios II , C/C++ Application, click "Next >" Select Project Template to Count Binary. Reassign Name: to "second_cpu_count_binary". defaults to correctly selected SOPC Builder System, so I didn&#39;t have to change it. Change "Select Target Hardware CPUa" to second_cpu. Press "Finish" (accept default of making a new system library for this). Back in Nios II IDE&#39;s main window, press the "Build all" icon. (Because I don&#39;t have any other software projects around, this is cool for me, but you might have some other projects sitting around that you don&#39;t want to rebuild) Nios II IDE, Running TRICKY: go to Window -> Preferences -> Nios II Run and Build Settings. Check the checkbox that says "Allow multiple active run/debug sessions", press "Apply", then "OK". Highlight "second_cpu_count_binary" in the left-hand pane labelled C/C++ projects. (having this highlighted allows defaults of next steps to come up correctly) Choose the menu item Run -> Debug... . We want to make a new run/debug configuration, so highlight "Nios II Hardware" and press "New". The name will default to "second_cpu_count_binary Nios II HW configuration", the project will be correctly set to "second_cpu_count_binary", the Nios II ELF Executable will correctly be set to "Debug/second_cpu_count_binary.elf". there is nothing you need to do on this page. Press the "Target Connection" tab, which (on my system) has a red X indicating that the values assigned to this tab are not correct. Choose the JTAG Cable that you are using (i used USB-Blaster). It is allowable to leave the JTAG Device as "automatic". The Nios II Terminal communications device should already be set to "second_jtag_uart". TRICKY: press the "Debugger" tab. choose a random 4-digit number for "TCP port for Debugger". This will be the port that the tool uses for second_cpu. This number has to be unique in that it does not conflict with whatever TCP port number you give the other cpu "cpu". This is expected to be an automatic step in Nios II IDE 1.1 Hit the "Debug" button. the program should download. N2IDE shifts to the Debugging perspective, and becomes halted when it hits the breakpoint at "main". press the "play icon to get the program running. it&#39;s not neccessary to have one cpu in any particular state while downloading/debugging the other(s). Go back to the C/C++ development perspective using the icon or =Window -> Open Perspective -> C/C++ Development=. Highlight the cpu_hello_world project. (again, having this highlighted merely allows defaults of next steps to come up correctly) Choose the menu item Run -> Debug... We want to make a new run/debug configuration, so highlight "Nios II Hardware" and press "New". The name will default to "cpu_hello_World Nios II HW configuration, the project will be correctly set to "cpu_hello_World", the Nios II ELF Executable will correctly be set to "Debug/cpu_hello_World.elf". there is nothing you need to do on this page. Press the "Target Connection" tab, which (on my system) has a red X indicating that the values assigned to this tab are not correct. Choose the JTAG Cable that you are using (i used USB-Blaster). It is allowable to leave the JTAG Device as "automatic". The Nios II Terminal communications device should already be set to "jtag_uart". Press the "Debugger" tab. you may either choose a random 4-digit number for "TCP port for Debugger", or leave the default value of 2342 if you had chosen a different number for second_cpu_count_binary. This will be the port that the tool uses for cpu cpu. This number has to be unique in that it does not conflict with whatever TCP port number you give the other cpus. Hit the "Debug" button. The program should download. N2IDE shifts to the Debugging perspective, and becomes halted when it hits the breakpoint at "main". You will note that both programs are running simultaneously on each of their cpus. You may halt/step/view each of the theads individually from here. I don&#39;t think there are any other steps to particular to debugging multiple cpus from here...

OK, more info. All cut and pasted (with bits moved and removed) from an email. For Nios I, there was no direct tool support for multiprocessor systems. The user could make multiple processors, but the tools had no inherent knowledge of how to keep them from interfering with each other. The customer is right that there is a lot of hand-massaging to do for Nios I. The best way to prevent conflict is to give the CPUs different reset and interrupt vectors (with enough room for code/vector table), and by targeting the SDKs to compile in different memory components, and to check the objdumps for overlap. Unless the customer is a master of GCC linking, this is probably the only thing they can do. For Nios II, the IDE (not the Legacy SDK) has a minimal knowledge of multiprocessor systems-- enough to prevent some basic conflicts. The CPUs still need to be set to different reset and interrupt vectors (very important that they are!). The exception address has a secondary function in that it is used by the Nios II IDE as a guideline on where to target elfs. I think if you set your exception address half-way through a memory, you&#39;ll find that the Nios II IDE will compile the elf for the area after the exception vector. When linking, the IDE does a better job of sharing memories between CPUs, but I&#39;m not certain exactly how.

multiple NIOS II cores | Altera Community

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Altera_Forum
Honored Contributor
20 years ago
--- Quote Start ---
originally posted by kerri@Sep 1 2004, 06:21 PM
ok, here's some instructions (nios ii).
--- Quote End ---

Hi. Your instructions were excellent. I followed them easily. But I'm having trouble getting my design running.

Here are my differences:
I'm running it on our own board with an EP2S60.
I created a simple Quartus project with nothing but a PLL, a little reset circuit and a NIOS block.
In SOPC builder I made it have 2 Nios processors, each of which has its own jtag_uart and 64K block of RAM. They are both NIOS II/s with Level 1 JTAG. I was very careful about the memory map and the instruction/data master connections. Note that I didn't share the memory and the blocks aren't continguous, either.

Keep it simple, right? The Nios block has two gazintas, clock and reset, and no gazoutas. Pretty hard to mess that up.

In the NIOS IDE I built two hello_world projects, one for each cpu. All they should do is print Hello from Nios II cpu_0/cpu_1 forever.

Following your directions for Debug mode, there were two differences between my configuration and yours.
First, when I open Run --> Debug there is a "Nios II Multiprocessor Collection" item in the list. Does that work yet?
Second, in Nios II Hardware --> hello_cpu_1 Nios II HW configuration --> Target Connection there was no entry for TCP port for Debugger. You pointed out that it might not be there, so no problem.

When I hit the Debug button, this message came up in the console:
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused

I did the same thing with cpu_0 and got a similar message.

The board works with a single cpu, so that's not the problem.

Any ideas?

Leslie

update 10/16:
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif
It bothered me enough to justify coming in to work today to figure it out. And of course it only took a half hour to get both processors running.
The answer was to uncheck Debug --> hello_cpu_1 Nios II HW configuration --> Debugger --> Break at Main().
I'll try to understand why I had to uncheck it when I write up what I did. I'm guessing it's because I haven't patched the IDE.

update 10/17:
Ack, it doesn't work this morning.
Any ideas?

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multiple NIOS II cores

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