Multiple CPU or Nios II?

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originally posted by stephenm@Apr 17 2006, 09:14 AM

2) i can create a second cpu internal to the sopc builder document. this cpu would be used exclusively to read the fifo and store the data into a dual port on chip memory.

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Hi Stephen,

One idea you may want to consider is rather than a second CPU to just copy data is to use a DMA with flow control which allows a slave port (your FIFO) to manage the flow of data to simple "unintelligent" masters like a DMA with some simple handshaking signals.

In that way the transfer of data from the FIFO is managed by an independet dma engine allowing the data to be buffered into a dual-port memory whenever the FIFO starts to get full (but this brings up the issue of what is the purpose of the FIFO if it overflows too often - I think a fifo is only useful to help manage "bursts" of data not as a storage area for a contant flow of data). This should free up your Nios to focus on processing data and transfering it to compact flash. There are probaby a few other areas in your "data processing" that could also be speed up with some hardware processing components using more DMAs or just the Nios shuffling data around the system.

Here are some references you can look at:

DMA component:

http://www.altera.com/literature/hb/nios2/n2cpu_nii51006.pdf (http://www.altera.com/literature/hb/nios2/n2cpu_nii51006.pdf)

For details on flow control see the Avalon Interface Specifications (Ch 6):

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

Hope this idea helps

Regards,

-ATJ