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Altera_Forum
Honored Contributor
Honored Contributormulticycle custom instruction not working
Hi All, I am trying a 3 cycle (fixed) multi cycle instruction module with nios2. below s my interface. port ( clk : in std_logic := '0'...
Altera_ForumHonored Contributor
Honored ContributorI'm no vhdl expert! but aren't you missing a test for the edge of 'clk' ?
