Altera_ForumHonored Contributor14 years agomulticycle custom instruction not working Hi All, I am trying a 3 cycle (fixed) multi cycle instruction module with nios2. below s my interface. port ( clk : in std_logic := '0'...Show More
Altera_ForumHonored Contributor14 years agoI'm no vhdl expert! but aren't you missing a test for the edge of 'clk' ?
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