Multicore boot out of epcs

As far as i had understood the epcs controler ip, when the fpga has finished fetching the image, it's internal pointer points to the first byte after the fpga image. and that byte is the first byte of your application image.

normaly the reset vector points to the epcs controler ip that has a memory block used as a boot code memory. that routine now copies one byte after another from the epcs device to the destination memory and after that starts to execute the code from that location.

so it will only copy your first ELF directly after the SOF

in fact both would copy the same bytes as they both start the epcs boot copier routine, and i guess that is your problem. i don't think that epcs routine will setup correct memory locations inside the epcs depending upon your cpu.

do both nios execute the boot copier routine at the same time ?

can you control the reset of these nios cores, that the onw with the first ELF starts first and the the next nios ?