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Altera_Forum's avatar
Altera_Forum
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15 years ago

Multi Nios

Hi folks.

I have a strong doubt, that my will not work and i want to avoid it.

In my system i have 2 Nios processors.I use EPCS flash memory, which stores 2 images.

First is woking with data, that FPGA provides him.Second is responsible for communication. I use Ethernet communication and we purchased TCP/IP stack.

I have to support the functionality of updating the first Nios,i mean to recompile all source code,to for Nios architecture and to prepeare NIOS1.flash image. Now the questions:

  1. May I to update the NIOS image without updating FGPA program?
  2. Is there any problem to use described above topology of NIOS processors?
  3. If I receive the new version for NIOS1 via Ethernet link, is there any problem to burn it to Flash(EPCS) memory?

P.S. Another question: Do I must to use for each one of images Boot loader, or enough to use one BL for all (2) NIOSs?

Thanks, Slava

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Slava, I'm using just one Nios but changing the content of EPCS over ethernet is implemented there.

    I will try answer your questions.

    1. Yes it's possible. You have to know the start address of the firmware image. The best is when it starts at a sector boundary.

    2. No idea

    3. No you can use the alt_write_flash_block() or alt_write_flash() function from Altera HAL API. Data transmission is more save if you use an additional checksum.

    Last Question: I think you have just one bootloader because only one EPCS device controller core can be instantiated in each FPGA design. The boot loader code is stored in a small onchip RAM in epcs controller.

    Jens
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hello,

    I am developing a multiprocessor project to compress the image. My proposed task is:

    I have designed two processor sytem on de2-70.Now I want each processor to compress half part( half horizontal slice) from the image simultaneously.

    I have tested the apllication for single processor image compression(png to jpeg image conversion)

    Can you please provide any suggestion regarding above task? I want to how to achieve interprocessor communication?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Actually, I think, more efficient solution will be to implement the compression algorithm by HW. I mean VHDL code. I still a new in Nios ll, but l know, you can determine shared memory between your processors.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You could map a block of M9K memory as tightly coupled data memory for both cpus.

    Use Decker's algorithm for mutual exclusion.