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Altera_Forum's avatar
Altera_Forum
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14 years ago

multi Nios connect to One Pcie

Hi, I'm trying to connect an array of Nios processors that are designed by Qsys to ONE Pcie (CycloneIV pcie ip compiler-completer only) module that is designed by SOPC. I'm going to send dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your replies.

After your advices, I redesign my system and I'm going to implement it in a single Qsys design and each cpu as a subdesign.

Is there any thing that i should care if i use one share memory for more than one cpu? (read while write and rtc.)

Is there any need to use some things like hardware mutex?

All my writes and reads to share memory, are done with IORD_32DIRECT and IOWR_32DIRECT. And i thinks these are atomic operation. Am i wright?

Does Avalon interface control these operations or I should use DMA?

Thanks.