Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
Our FPGA Design contains total 4 MSI-X Interrupt Table Size and I have passed "nr_entries=4" in pcie_enable_msix function which successfully executed without any issue. Good News is that I am able to get MSI-X Interrupt successfully in my Linux Host Machine by changing "Avalon MM Address Width" to 64 instead of 32 as we have analyzed that MSB bit of MSI-X Structure Address is chaanged while using 32 bit Address Width (means value of MSI-X Structure Address is changed from 0xFEE0C000 to 0x7EE0C000). So, PCIe IP Core is not able to generate MSI-X Interrupt due to MSI-X Structure Address mismatched. I have also contacted to Altera Service Request and confirmed that I need to set Avalon MM Width to 64 to use MSI-X Interrupt and it won't work in 32 bit Avalon MM Address Width. Regards, Ritesh Prajapati