Altera_ForumHonored Contributor12 years agomSGDMA write master FIFO query Hi, I recently asked a question about the mSGDMA on this forum here (http://www.alteraforum.com/forum/showthread.php?t=44113&p=183258#post183258). But I'm starting a new thread as I think the issu...Show More
Altera_ForumHonored Contributor12 years agoI've fixed this issue by changing the write master data width and burst settings.
Recent DiscussionsError generating BSPSolvedNIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)SolvedWhere is FreeRTOS-Plus-TCP DesignSolvedNIOS-V QSYS Warning Properties (associatedClock) have been set onSolvedDK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails