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Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- I do control mSGDMA with lightweight AXI In QSys: CSR, Descriptor, Response connected to lw_axi_master mm_write connected to f2h_axi_slave In Linux: open /dev/mem mmap to 0xFF200000 with offset of registers addresses --- Quote End --- Great. See, that makes sense. f2h_axi_slave, or f2h_sdram? Where are you pushing data?