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Altera_Forum
Honored Contributor
Honored ContributormSGDMA and On-chip Memory
Hi all! I'm creating a design that uses a Nios II processor with on board memory and wish to be able to read & write to the on-chip memory from custom Verilog. I did originally try using ...
Altera_ForumHonored Contributor
Honored ContributorHi BadOmen,
I am quite new with Quartus. So basically, I used Qsys to generate my hps component ans my system. I created 2 slave component(read and write) ( avalon memory mapped slave) and i can through the lightweight HPS-to-FPGA bridge map the address of the first slave (write) and write data. Also with the second one i can read data from it by the hps. The problem is that the lightweight HPS-to-FPGA bridge has a capacity of 32 bits. So now, I would like to use the HPS-to-FPGA bridge which has a capacity of 128 bits. I did the same thing that i did for the lightweight. but it doesn't work. I don't know why?? What is the difference between those two bridges? is there something to add (configuration)? Could you please help me out from it?? It will be your great help!!
