Altera_ForumHonored Contributor14 years agoModify SDRAM Controller Cyclone ii - DE1 Hi, I generated a SDRAM Controller using the guide "Using the SDRAM on Altera’s DE1 Board with VHDL Designs". This guide illustrate how to create a SDRAM Controller using SOPC builder in Quartus...Show MoreSDRAM_CONTROLLER.JPG130 KB
Recent DiscussionsLPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 ProNios V/m JTAG run‑control HALT fails — Debug Module healthy, hart never haltsNIOS II "Verify failed" for on-chip memory 128kTest PostError generating BSPSolved