Forum Discussion
Altera_Forum
Honored Contributor
20 years ago --- Quote Start --- originally posted by alexs@Apr 16 2006, 10:47 PM hello experts http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif
i want to bring this topic up again !
how simulate nios2 5.1 in modelsim ?
this feature is not work !!!!
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--- Quote End --- Hi AlexS, I took a look at your diagram and it seems that the d_irq signal that feeds into the Nios II CPU looks to have a Z input right after the reset signal is released (0000000Z'b). I would expect simulation to "fail" when an undefined input is driven into logic. Everything on the Nios II processor goes to high-impedence (red) after that Z input to the d_irq from the system inputs. I would consider looking at all your components that use irq to the Nios II processor to trace back their source. One idea may be to remove each component from the system to see if the problem goes away. Regards, -ATJ