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Altera_Forum's avatar
Altera_Forum
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14 years ago

Measuring time in vhdl

Hi all,

I am using a FPGA to control two external FIFOs to receive inputs from 2 non sync cameras. These inputs will be sent to DSP for image processing. I need to build a sort of a timer to measure the time lag between the inputs to ensure that both cameras are recording the same images.

I saw some code on how to measure time in VHDL but I don't think that they're synthesisable. Does anybody know how to do this?

Many thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Best thing to do would be to build a frame synchroniser using external ram. You need external ram because you need to be able to store two whole fields/frames from both sources in memory. You need it double buffered so you are always reading from one while writing to the other. You may even need it triple buffered to cope with them being out of sync. This way you know you are always processing the same frames in parrallel.

    Otherwise you could just count the clock cycles between the syncs. The only problem with it is that it is likely to drift over time.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Best thing to do would be to build a frame synchroniser using external ram. You need external ram because you need to be able to store two whole fields/frames from both sources in memory. You need it double buffered so you are always reading from one while writing to the other. You may even need it triple buffered to cope with them being out of sync. This way you know you are always processing the same frames in parrallel.

    --- Quote End ---

    I'll be using those FIFOs as external RAMs. Actually the cameras' inputs will be written into the FIFO, not to the FPGA. I am using the FPGA to control the FIFOs reads and writes.

    I was also thinking of a double-buffered solution, but the FIFOs I found do not have these features. How about "simultaneous read and write ports"? (Found it on a Cypress 18Mbit programmable FIFOs).