Max throughput of SOPC DMA?

Hi, thanks for all the help so far.

Aren’t I already sending multiple descriptors into it then? Since I fill the FIFO with descriptors (waiting on the FIFO to have room for another descriptor) and after that I wait for the last word to be written by the SG-DMA, which causes an interrupt?

The actual data transfer is what takes up almost all the time, ofcourse.

I changed the burst count to 64 (the maximum for RapidIO) and the FIFO depth for the SGDMA to 512. And I enabled the "Full word access only". But that made zero difference, it even seemed to get slightly slower? With 1024 words burst transfer the FIFO depth was 2048.

For the record the ~360 MB/s is the transfer speed between 2 on-chip memories at the moment. The transfer speed from on-chip memory to RapidIO is somewhat slower.

(Maybe these DMA controllers simply aren't good at sending small amounts of data (32k) per descriptor? )

Edit: With transfers of 60k I get exactly the same transfer speed, so that doesn't (really) seem to matter.

Or there might be something I do wrong in the software (even though I think it's the same as the example)?

Please see the attached picture for the configuration. The on-chip RAMs are the standard SOPC builder memories. They are 32 bits wide.