Max throughput of SOPC DMA?

If I only add one (since the buffer is able to store 128 descriptors):

while ((read_csr_status(MODULAR_SGDMA_ONCHIP_CSR_BASE) & CSR_DESCRIPTOR_BUFFER_FULL_MASK) != 0) {} 

and then 128 times

write_standard_descriptor (MODULAR_SGDMA_ONCHIP_CSR_BASE, MODULAR_SGDMA_ONCHIP_DESCRIPTOR_SLAVE_BASE, a_descriptor_ptr) ;

in the for loop.

I get a maximum throughput of 3760MB/s (did a miscalculation earlier).

The data does seem to get transfered though, if in the middle of those 128 'write_standard_descriptors' I clear the RX memory and after one 'write_standard_descriptor' I read it back out again.

Edit: Something still goes wrong with calculation, since when I double the transfer_size, the number of clock_ticks double but the transfer size decreases.

Edit2: I'm running towards the maximum I can store in an unsigned long I think >,<.

Edit3: Yup, was going over 2^32.

Edit4: Calculating gives:

Test completed with a transfer size of 40000MB

Transfer time (clocks ticks): 83374115

Transfer time (seconds): 0.833741

This gives a throughput of 47962MB/s

which means with a clock of 100 mhz a throughput of 47962 mb/s , now that can't be right or can it?

Edit5: Ah if I wrap an IF around it

 
if(write_standard_descriptor (MODULAR_SGDMA_ONCHIP_CSR_BASE, MODULAR_SGDMA_ONCHIP_DESCRIPTOR_SLAVE_BASE, a_descriptor_ptr) != 0)
{
printf("Failed to write descriptor 0x%lx to the descriptor SGDMA port.%c", i+1, TERMINAL_KILL_CHARACTER);
}

I get Failed to write descriptor 0x42 to the descriptor SGD.

I have to add

 
while ((RD_CSR_STATUS(MODULAR_SGDMA_ONCHIP_CSR_BASE) & CSR_DESCRIPTOR_BUFFER_FULL_MASK) != 0) {} // spin until there is room for another descriptor to be written to the SGDMA

between each write_standard_descriptor .