making an IP for DMA transfers

We have the mSGDMA operating in continuous DMA mode and start and stop under NIOS software control using a seperate VHDL module to detect the trigger events and count samples from there. In continuous mode the mSGDMA wraps around the assigned address space without problems.

Should mention that proper capture of DMA data to the DDR3 controller requires using the faster of the two DDR3 controller output clocks to run the internal qsys DCFIFO.

The assumption that a regular megawizard FIFO can function as a streaming interface model in simulations seems to work out. The FIFO has to be in look ahead mode for the simple hookup. I got the normal synchronous mode to work using some extra glue logic but a casual search did not locate documentation to confirm using that design as a streaming model.