making an IP for DMA transfers

The Qsys OnChip FIFO interface is ready, valid, and data[31..0]

Planning to connect Qsys:ready--> DCFIFO:rdreq

and DCFIFO:empty --> NOT--> Qsys:valid

That seems to work using a DCFIFO --> SCFIFO test design.

Assumptions based on documentation that OnChip FIFO implements an SCFIFO for single clock option.

I attended a Qsys workshop a couple of months ago and have a copy of mSGDMA (from PCIe example) in the files ... so installed a write master and dispatcher hooked up with ST export. Sure enough got the same 3 ... ready, valid, and data[31..0]