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Altera_Forum's avatar
Altera_Forum
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14 years ago

making an IP for DMA transfers

Hello everybody. I work with the Terasic DE2-115. I'm trying to plug the TRDB-D5M camera on a NIOS II with ethernet. I can read data from the camera with the IP given by terasic, and I can us...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The Qsys OnChip FIFO interface is ready, valid, and data[31..0]

Planning to connect Qsys:ready--> DCFIFO:rdreq

and DCFIFO:empty --> NOT--> Qsys:valid

That seems to work using a DCFIFO --> SCFIFO test design.

Assumptions based on documentation that OnChip FIFO implements an SCFIFO for single clock option.

I attended a Qsys workshop a couple of months ago and have a copy of mSGDMA (from PCIe example) in the files ... so installed a write master and dispatcher hooked up with ST export. Sure enough got the same 3 ... ready, valid, and data[31..0]