Altera_ForumHonored Contributor16 years agom_state == STATE_DEBUG Error I build a SOPC system which consists of a Nios II cpu, onchip memory and jtag uart component with frequency of 100MHz driving all the components. The system works fine when I run the count binary pro...Show More
Altera_ForumHonored Contributor15 years agoMaybe this could help http://www.altera.com/support/kdb/solutions/rd05242010_978.html
Recent DiscussionsMultiple NIOS V ImplementationSolvednot able to use multiple niosV cores at the same timeNios V/m JTAG run‑control HALT fails — Debug Module healthy, hart never haltsSysID TimestampImplementing many Nios® V cores on Agilex™ 7