Hi,
we are experiencing the same issue with the Cyclone 10GX evaluation board. If I understood correctly this seems to be a hardware bug of the evaluation board, as there is no LVDS clock connected to the bank 2L where the Ethernet Core is connected to?
The clock "C10_REFCLK1p" (n) which is used in the simple socket example uses another bank and the clock "C10_REFCLK2p" (n) is connected to pins G23 & F23, which don't support LVDS.
According to the following post, the LVDS SERDES IP requires a LVDS clock on the same bank.
https://forums.intel.com/s/question/0D50P000043o6Ro/lvds-serdes-reference-clock-enforcement-change-in-181?language=de
Best Regards
New Contributor
