Forum Discussion
VRama10
New Contributor
New ContributorLVDS error in 18.1 while using Triple Speed Ethernet IP
Hi, I'm a beginner with Nios II platform designer. I was using an example project from Intel built for Cyclone 10 GX board using Quartus 17.1. It was working fine. As I need to integrate this des...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorHello ,
Sorry.I am bit confused with your input . To make sure , are you using the same design for 17.1 and 18.1 ? from the Error it looks like PLL channel mapping issue.
Do you getting this error during fitter right ?
Would it possible to share the design if it is not confidential ? that make my life easy :)
Thank you ,
regards,
Sree
VRama10New Contributor
New ContributorPlease let me know if you any updates on this issue.
