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dim1's avatar
dim1
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2 months ago
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LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro

Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But...
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Nios Architecture
  • LiangYuG_Altera's avatar
    LiangYuG_Altera
    10 days ago

    Hi dim1​ 

    Got it.

    (This may come rather late for you, sorry about that. But I believe you will be interested in this new findings.)

    There is another workaround for the Agilex 5 & 3 EMIF IP involving the isMemoryDevice agent information.

    You may refer to this KDB.

    Unlike the Add Memory Device workaround, this one is tied to QSYS. As such, isMemoryDevice workaround (repeat per new QSYS) is less repetitive compared Add Memory Device workaround (repeat per new BSP).

    Besides that, the isMemoryDevice workaround fixes the problem from the roots in Platform Designer. Thus, the subsequent BSP Editor will work seamlessly (the experience of EMIF IP in BSP Editor will be akin to a OCRAM IP). 

    Regards,
    Liang Yu

dim1's avatar
dim1
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26 days ago

Hello Liang Yu,

Thank you for your reply. Will try Quartus Prime 26.1.1 Pro once it is available.

Best regards,

D.

dim1's avatar
dim1
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11 days ago

Hello Liang Yu,

So I tried to manually add linker memory device, following the steps in the link you provided. Unfortunately, it does not work. What happens is, a second, duplicate device is created, and still not accessible for creating linker regions, section mappings etc.

Here is how the memory map looks originally. The EMIF IP is shown as lpddr4_s0_axi4:

I add a new Memory Device, with name lpddr4_s0_axi4,  Base Address 0 and Size 0x80000000.

This results in the following Memory Map:

Notice how now there are two lpddr4_s0_axi4 devices, and neither one of them is usable in the BSP Linker Script.

Please advise.

Thank you,

D.