Looking for tips on how to implement variable length data transformation / parsing.

rbugalho,

You understood my problem correctly. Thank you very much for the response. It clarifiers things a lot. The smoke was coming out of my head thinking if that's OK to pause or not and if there is a way not to do so or not.

The user logic, I think, will be running at around 300, maybe 330 MHz. The data will be coming from the double-clock FIFO. Most of the time data rate will be a lot smaller, but I am hoping for the best while preparing for the worst.

I guess I will just sketch up a simple state machine with minimal pipelining first (to keep it simple) that pauses the sink interface and does what it needs to do. Then describe timing constraints and try to synthesize it. If the timing will not be met, will introduce more pipeline stages until I achieve a logic that can handle the maximum load.

Thank you very much for your response!