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The on-chip memory is configured in Dual port mode, the 2nd interface is exported outside NIOS II in order to be accessible via my custom FPGA logic.
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Are You using QSYS?
What exactly signals are exported from the 2nd interface of on-chip memory in dual-port mode?
I see the following:
https://www.alteraforum.com/forum/attachment.php?attachmentid=7952 What is a Write2 signal? Is it WriteEnable?
And why the Read2 is missing?
How then to read from on-chip memory via my custom FPGA logic?
Where can I find the detailed description of all exported signals for Altera On-chip memory IP?
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