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Hi,
I have a little bit doubt that Nios CPU with MMU can't have over 4Kbytes caches. There are several ways of connecting method for CPU, cache and MMU. For example,
1) CPU -- cache -- MMU -- Memory
2) CPU -- MMU -- cache -- Memory.
The first method has low latency, but also has 'synonym problems'. The second method accesses the cache by physical addresses, but has larger latency to the contrary. So I think that Nios CPU takes the next strategy i.e.
3) CPU |--cache --| -- Memory
............|--MMU --|
by limiting the size of cache under page size.(Please refer Nios handbook n2cpu_nii5v1.pdf, page 2-10, Figure 2-2.)
If so, we can't have both instruction and data caches larger than page size(=4Kbytes).
Kazu
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I found the relevant section, page 3-53 of the handbook:
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Virtual Address Aliasing
A virtual address alias occurs when two virtual addresses map to the same physical
address. When an MMU and caches are present and the caches are larger than a page
(4 KBytes), the operating system must prevent illegal virtual address aliases. Because
the caches are virtually-indexed and physically-tagged, a portion of the virtual
address is used to select the cache line. If the cache is 4 KBytes or less in size, the
portion of the virtual address used to select the cache line fits with bits 11:0 of the
virtual address which have the same value as bits 11:0 of the physical address (they
are untranslated bits of the page offset). However, if the cache is larger than 4 KBytes,
bits beyond the page offset (bits 12 and up) are used to select the cache line and these
bits are allowed to be different than the corresponding physical address.
For example, in a 64 KByte direct-mapped cache with a 16-byte line, bits 15:4 are used
to select the line. Assume that virtual address 0x1000 is mapped to physical address
0xF000 and virtual address 0x2000 is also mapped to physical address 0xF000.
This is an illegal virtual address alias because accesses to virtual address 0x1000 use
line 0x1 and accesses to virtual address 0x2000 use line 0x2 even though they map to
the same physical address. This results in two copies of the same physical address in
the cache. With an n-byte direct-mapped cache, there could be n/4096 copies of the
same physical address in the cache if illegal virtual address aliases are not prevented.
The bits of the virtual address that are used to select the line and are translated bits
(bits 12 and up) are known as the color of the address. An operating system avoids
illegal virtual address aliases by ensuring that if multiple virtual addresses map the
same physical address, the virtual addresses have the same color. Note though, the
color of the virtual addresses does not need to be the same as the color as the physical
address because the cache tag contains all the bits of the PFN.
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Question is is this support implemented in Linux and what would be required to fix it.
Honored Contributor
