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I have a little bit doubt that Nios CPU with MMU can't have over 4Kbytes caches. There are several ways of connecting method for CPU, cache and MMU. For example,
1) CPU -- cache -- MMU -- Memory
2) CPU -- MMU -- cache -- Memory.
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I asked Frank Storm our dealer's Altera FPGA. He said that the reference designs of Altera's do have 2*32K Cache and Altera recommends not not change the cache configuration. So the 4K limit does not seem to exist. Nonetheless I asked him to doublecheck the NIOS MMU/Cache "hardware" regarding this issue.
-Michael
Honored Contributor
