--- Quote Start ---
Hmmm, AFAIR, the hardware manual states that with MMU, bit 31 is not use for cache enabling purpose, but that you need to create dedicated MMU pages for non-caching accesses (with the appropriate cacheable bit setting in the page descriptor). But of course nobody prevents you from defining all pages with the virtual address bit 31 set as non-cacheable. I have no idea how all this is done in the Kernel code.
-Michael
--- Quote End ---
OK, I found the manual (
http://www.altera.com/literature/hb/nios2/n2cpu_nii51003.pdf), and you are right, bit 31 is not used that way. However, virtual addresses 0xe0000000 and above are are mapped for I/O, skipping the TLB and the cache. So the behavior of ioremap is correct.