Linux with MMU on NEEK

Hi,

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I had the cache changed in the custom design to the minimum as in the NEEK design (it was 8+8k) and the ethernet works now. *headdesk*

My theory is something isn't getting flagged properly for uncached IO and using the smaller cache just happens to avoid caching those bits.

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I have a little bit doubt that Nios CPU with MMU can't have over 4Kbytes caches. There are several ways of connecting method for CPU, cache and MMU. For example,

1) CPU -- cache -- MMU -- Memory

2) CPU -- MMU -- cache -- Memory.

The first method has low latency, but also has 'synonym problems'. The second method accesses the cache by physical addresses, but has larger latency to the contrary. So I think that Nios CPU takes the next strategy i.e.

3) CPU |--cache --| -- Memory

............|--MMU --|

by limiting the size of cache under page size.(Please refer Nios handbook n2cpu_nii5v1.pdf, page 2-10, Figure 2-2.)

If so, we can't have both instruction and data caches larger than page size(=4Kbytes).

Kazu