LAN91C111 reference hardware design

Ok, so I found what I was looking for, it was under the discontinued products.

http://www.altera.com/products/devkits/altera/kit-niosii-2s60.html

If I am reading the schematics correctly, they appear to share an address and data bus between the LAN91C111 and the flash. To me this says you can trade bandwidth to the components on the tri-state bridge for pin count. This may be exactly what I need.

David

David,

While I can't tell you how the soft MAC vs LAN91C111 hard MAC differs to the OS / Driver, I can tell you my experience with the device.

Check out page 5 of the schematic below. It shows all the address lines connected up, but you don't need to connect all of them. The LAN91C111 responds to a base address of 0x300. There are many ways to write packet data into the chip. I chose to have a 32-bit data path (though, I believe you can use a 16 bit path as well). The entire address space of the chip is rather small in this configuration. Look at Chapter 8 in the LAN91C111 datasheet. I believe the entire space is only 16 locations. The chip uses a banking register to increase the space (performance limitation).

I had an FPGA directly connected to the chip. I did not use a CPU, but instead chose to use a state machine to write data into the chip. It was pretty easy and I had a working setup in the lab in a week. But, to get to that point, I took the LAN91C111 datasheet everywhere I went and read it several times.

There's source code out there too, and I imagine it would be pretty easy to write a driver for this device. One word of caution - there are throughput limitations. For my design, I didn't need a lot of throughput - a couple Mbps. But, if you are expecting to get the full line rate, you have some work to do.

Please note that it has been years since I looked at this, so double check what I've said.

Links to follow in another post....

LAN91C111 datasheet:

http://www.rennes.supelec.fr/ren/fi/elec/ftp/fpga/altera/nios_stratix/datasheet/lan91c111.pdf

Manual:

http://www.altera.com/literature/manual/mnl_nios2_board_cyclone_1c20.pdf

Schematic:

ftp://ftp.altera.com/outgoing/download/support/ip/processors/nios2/nios_cyclone_1c20/nios_1c20_board_schematic.pdf

Thanks for the link. Funny you mention the state machine approach because the vast majority of my design is state machine based. I too have a very low data rate need, I am currently fitting all of my data (without much protocol overhead) into a 460 Kbps RS-422 line.

Probably for electrical isolation issues, we need to locate the ethernet magnetics on a separate board away from the main FPGA board. I wonder if I could make this chip work on a separate board.

Anyway, thank you very much. If you still have state machine code to interface to this chip handy, I would be interested.

David

If your data rate is under 1Mbps, you could probably just run the interface at 10Mbps (versus 100). This leads into the issue of putting the magnetics on a seperate board. Generally, when you are running "high speed" signals, you want to keep traces short. In your case, keeping the magnetics close to the chip. But you have some isolation concerns - are you referring to isolation from the standpoint of high voltage / PCB dielectric breakdown? Or are you worried about digital signals contaminating the Ethernet signals (crosstalk)? Be careful with running these traces off-board - especially if you intend to run at 100Mbps. There are many ways for a designer to connect two boards - flex circuits, cables, connectors. Whatever solution you decide to use, you should perform a signal integrity analysis. Also, the design of the PCB near and around the magnetics is usually very specific (at least it is for GigE). For example, not having any other signals (except the ones from the PHY) on any other layer below the magnetics. Some recommend having a nice clean ground plane under the PHY - others recommend not having one. The best thing to do is read the device datasheet, and contact the manufacturer. Some will critique your PCB design free of charge to make sure it looks OK. Personally, I would keep the magnetics right next to the PHY - but in your case, I don't fully understand the specific requirements / circumstances that you are facing.

I wish I could provide you with the state machine code I had, but that is the property of my employer and I'd be in big trouble if I made it available (even though the code is so simple that it's like patenting 1+1 = 2). Have a look at section 10.3 and 10.4 (transmitting and receiving a packet) in the LAN91C111 datasheet. I implemented those exact routines. Section 8 is your friend. You'll probably need to read it several times before things start to sink in - at least that's what I needed to do.

For example, to start the Receive process, you might have something like this:

-- Set Bank register to 0:

WHEN State0 =>

nWR <= '0';

Address <= X"30E";

Data <= X"0000";

Next_State <= State1;

WHEN State1 =>

nWR <= '1';

Address <= X"30E";

Data <= X"0000";

Next_State <= State2;

-- Set RXEN to 1, as stated in 10.4

WHEN State2 =>

nWR <= '0';

Address <= X"304";

Data <= X"0001";

Next_State <= State3;

WHEN State3 =>

nWR <= '1';

Address <= X"304";

Data <= X"0001";

Next_State <= State4;

....

I think you get the idea..