lan91c111 and custom board

Hello,

We are using a 16-bit implementation of the smc lan91c111 chip on a custom board and are not sure about how to assign the pins for the control signals in Quartus. The SOPC Builder component (non-Daughter-card implementation) gives access to the input signal IRQ and output signals IOR, IOW, RESET, ADDR[0]-ADDR[15], BE[0]-BE[3] and DATA[0]-DATA[31] to/from the block diagram in the Quartus top-level schematic. On our custom board, BE2 and BE3 are tied high through a 10k pull-up resistor since we are using only 16 bits of the data bus. We are not using CFI flash.

In the standard.qpf example project for the Nios Development Board, Cyclone II Edition, there are two control signals, nADS and AEN, that are separate from the block diagram and tied low in the Quartus top-level. These are the only control signals that are accounted for that allow the 91c111 chip to work on the dev board. There are also other control signals on the 91c111 chip though that could/should be relevant: LCLK, ARDY, nRDYRTN, nSRDY, INTR0, nLDEV, nDATACS, nCYCLE, W/nR and nVLBUS. In the dev board implementation, these signals do not show up in the Pin Planner, and so, don't seem to be accounted for in Quartus. We are assuming that since they are hardwired to specific pins on the EP2C35F672, that these FPGA pins will always accommodate the 91c111 control signals?? On the custom board, we are using an EP2C8Q208. We haven't been able to find any documentation that mentions what to do with these signals in Quartus.

Thanks.