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Altera_Forum
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15 years ago

JTAG UART & nios2-terminal comm problems

All--

I've got a JTAG UART issue I'm running into and I'm hoping someone out there might be able to help out. For whatever reason, nios2-terminal loses connection on an intermittent basis. It can take a minute upwards to 10 minutes but it always fails, giving me the error:

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nios2-terminal: exiting due to I/O error communicating with target

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My system consists of an EP3C55 Cyclone III part. SOPC builder is configured with JTAG UART, NIOS II/f, an SRAM component, a FLASH CFI component, and several other items. I'm connected to the target through a USB-Blaster.

I don't believe it is a FPGA configuration issue. I've used the Quartus programmer to simply load in the .sof file and then connected via nios2-terminal (without loading any sort of .elf file or executing code), and I see the error.

If I proceed with loading in an .elf file and execute my NIOS code, the code continues to work correctly in spite of the communication loss. When I execute nios2-terminal after a connection error, connections re-establish and the JTAG UART comms run again (at least for a while.)

Any ideas? We are connecting from the USB Blaster to the board using a connector interface that has been kludge-wired. I'm suspecting that this may be inducing some noise and the source of our trouble, but it's hard to definitely say that is the cause.

Thanks,

--tim

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    My first guess would be some bit errors on the JTAG signals too. Something occurring so rarely that you don't see it when downloading but have it after a while on the UART.

    You could try to check the signals with a scope. Pay attention especially to the JTAG clock, as over/undershoots could be seen as an additional clock edge by the hardware, and that could induce errors on the communication.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    We did some preliminary scoping on the various JTAG lines and then compared that to what we saw with the starter board. We didn't see much difference to be honest.

    We had an FAE in yesterday for some training and to look at our design. He saw two things that might be mitigating factors -- inductance from the kludge-wires may be to blame, and we are using a Terasic USB Blaster rather than an Altera branded USB Blaster. He mentioned that the signals between the Terasic USB Blaster and the device may not be as clean as they would be with an Altera USB Blaster due to cabling. We are going to get a loaner Altera USB Blaster to see if that improves things.

    I'll post results from that testing and if I learn anymore.

    --tim