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Honored Contributor
Honored ContributorJTAG conflict when debugging dual NiosII system
We have a dual NiosII arhitecture implemented on a Altera StratixIII dev. kit. The processors only share a dual port ram for communciation, i.e. each (cpuA and cpuB) has its own ram and rom, everythi...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Make sure to load the .jdi file for each application project before debugging the code. --- Quote End --- spot on! Thanks a lot.
