Forum Discussion
Altera_Forum
Honored Contributor
11 years agoSo now I noticed that the TCLK was going low twice as long as it was going high. I found that in the code and commented it out (not sure why it was there) and that sped up the clk to 50kHz from 33kHz. However, it still takes about 11 min to configure the FPGA and about 8 min to program the EEPROM device.
Could it be taking so long because of the size on the Cyclone V device?