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Altera_Forum
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12 years ago

Jam STAPL Byte-Code Player TCK Speed Slow

I am using a the Jam STAPL Byte-Code Player Version 2.2 code provided by Altera (found here https://www.altera.com/download/legacy/jam/dnl-byte_code_player.jsp) and some custom software to configure ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

So now I noticed that the TCLK was going low twice as long as it was going high. I found that in the code and commented it out (not sure why it was there) and that sped up the clk to 50kHz from 33kHz. However, it still takes about 11 min to configure the FPGA and about 8 min to program the EEPROM device.

Could it be taking so long because of the size on the Cyclone V device?