Issues with Quartis...

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originally posted by dcurry@Nov 10 2005, 07:52 AM

vitzh,

your vhdl coding style sucks, sorry man! compiling vhdl for simulation is much different than synthesis.

look at your code, can you draw a circuit from it? if no, then neither can your synthesis tool, or if it can, you probably wont get what you were hoping for.

vhdl is not c/c++, it doesn't execute line1, line2, etc... i looked over you code very briefly it's messy and doesn't make much sense, sorry man but that is probably what your synthesis tool is trying to tell you.

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lol. Unfortune, but true. Its been a year+ since I have done anything in VHDL. I have now changed how the code works to try to remove race conditions and only update one variable per clock cycle. Its working better now.

My only real question now is where can I find out the critical delay path of the synthesized circuit so I can determine the max. clock frequency?