Issues with Quartis...

vitzh,

Your VHDL coding style sucks, sorry man! Compiling VHDL for simulation is much different than synthesis.

Look at your code, can you draw a circuit from it? If no, then neither can your synthesis tool, or if it can, you probably wont get what you were hoping for.

VHDL is not C/C++, it doesn't execute line1, line2, etc... I looked over you code very briefly it's messy and doesn't make much sense, sorry man but that is probably what your synthesis tool is trying to tell you.

Start with some simple stuff, create a state machine to toggle a bit or something.

Real quick, 2 state machine implementations, both have 9 states, but will be synthesized differently.

--

-- This will give you a binary state machine with 9 states when synthesized.

--

subtype Sreg0_type is STD_LOGIC_VECTOR (0 to 3);

constant S1: Sreg0_type := "0000";

constant S2: Sreg0_type := "0001";

constant S3: Sreg0_type := "0010";

constant S4: Sreg0_type := "0011";

constant S5: Sreg0_type := "0100";

constant S6: Sreg0_type := "0101";

constant S7: Sreg0_type := "0110";

constant S8: Sreg0_type := "0111";

constant S9: Sreg0_type := "1000";

signal Sreg0: Sreg0_type;

-----------------------------------------------------------------------------------

--

-- This will give you a one-hot state machine when synthesized.

--

subtype Sreg0_type is STD_LOGIC_VECTOR (0 to 8);

constant S1: Sreg0_type := "000000001";

constant S2: Sreg0_type := "000000010";

constant S3: Sreg0_type := "000000100";

constant S4: Sreg0_type := "000001000";

constant S5: Sreg0_type := "000010000";

constant S6: Sreg0_type := "000100000";

constant S7: Sreg0_type := "001000000";

constant S8: Sreg0_type := "010000000";

constant S9: Sreg0_type := "100000000";

signal Sreg0: Sreg0_type;

Doug