Honored Contributor
Honored Contributoryour pll generates 2 clocks
C0 50MHz SDRamClk +90degree phase shift C1 50MHz Sysclock first of all i would change the phase shift from +90 to -45, thats a value we use from 48 up to 64MHz SDRam and the phase calculations acc. to the app.note A??? gives results in that area. but you should check the timing relation between your sdram clock and nRAS. the clock edge needs to be in the middle. not shure if it is the pos edge. see sdram chip data sheet with quartus 9.1 i can't open the sopc section of your design. so i can't give you more informations here. sorry. i can't find the *.sopcinfo file. next step ... limit the current strength for the sdram interface with the assignment editor. depending on your target, i would start with 12mA. this helps preventing over and undershots on those signals.
