Issue with polling in Nios

For your second question, if you can tolerate latency then I think a FIFO and interrupts will probably be your best bet (I'm not certain because I don't know exactly what you are doing).

Say you are moving data at a high rate from custom logic into the Nios II core, you would want the data buffered into a FIFO that supports a 'fill level'. A fill level can be something like the FIFO being half full, or 64 words buffered, etc... Once the fill level is hit because you choose what the fill level is set to you can have the CPU rapidly read data to drain the FIFO contents. The tricky part is making sure that you handle corner cases like Nios II emptying the FIFO just as fast as it's filling and potentially an interrupt being missed as a result. That's easily solved but that's the sort of thing you need to remember when you have events in your system.

Often when the data rate becomes too high you rely on DMA engines that will move the data into memory so that Nios II can access it directly, and the DMA engine would be responsible for letting the CPU know when the data has been stored to memory.