Forum Discussion
Altera_Forum
Honored Contributor
11 years agoGlad it could help you. And just like dsl said.... My problem was all in how the ISR was handled, the code was fine--I had effectively shot myself in the foot with the NIOSII configuraiton (lots of cache/etc..) That's what makes problems like I had so complicated to fix... there was nothing wrong with the 'C'... it was in how I had configured the NIOSII and the UART... enlarging the buffer and leaving the CPU alone, I was able to run all the way up to 250Kbps (which is the limit of the DE2-115 level converter--e.g. as fast as my hardware could support.. the FPGA/NIOSII/UART could have gone faster.)