ISR driven UART is missing characters (even at 9600bps... same prob at 230400)

If you configure the nios to have all its code and 'normal' data in tightly coupled memory, ensure everything is compiled with -O3, and avoid using any of the Altera HAL/libc code then you can do quite a lot with a 100MHz cpu (and run 1 instruction almost every clock).

If does take a little effort to stop gcc generating code that has pipeline stalls following memory reads (I don't thing the model that gcc is working on is correct).

There is also a hidden config menu for the nios cpu that lets you (amongst other things) generate a /f without the dynamic branch prediction login. This is needed if you really want to guarantee the execution time.

The altera docs do not make it 100% clear that the cpu stalls for the full duration of any Avalon cycle - even writes are not 'posted'.

The only undocumented stall I've found is a single cycle stall when a read from a tightly coupled data block immediately follows a write to the same block (both addresses would have to be presented at the same time!).