ISR driven UART is missing characters (even at 9600bps... same prob at 230400)

The JTAG debugger uses interrupts, NFI how often or how long they'll run with interrupts disabled.

The nios cpu itself is capabable of almost zero interrupt latency (use a separate register bank for the ISR).

The Altera HAL interrupt entry/exit code is another matter entirely! There could be a lot of instructions between the cpu taking the interrupt and your ISR actually running.

OTOH 2-3ms does seem an awful lot.