Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThanks dsl.
I think that the UART CORE is spotting the start-bits--mostly. (there's never garbage in the ring-buffer). But, I'd expect framing errors if it was seeing activity on the bus and not getting start/stop bits where the CORE expected them. But I don't get any "Frame Errors" in the status registers. And based on the documentation of the module, I don't see a way to disable that feature, so it should be capable of generating them if I unmask/configure them. What I'm observing is that hyperterminal in windows (and cutecom in linux) never miss anything from the device I'm trying to use with the FPGA... even up to ridiculous baud rates like over 900K... The DE2-115 board's level converters aren't rated for those speeds, but 9600bps... and 230400bps are well within the 250kbps rating of the devices... I'm really starting to lose hair on this...