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Altera_Forum
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16 years ago

is there any SOPC and NIOS2 design example of eeprom at93c46

in my design , i used one chip of eeprom: atmel 's at93c46, this memory 's interface looks like SPI interface. it has CS, CLK,DO and DI , but after reading it pdf document. i found it does accord wit...
Altera_Forum's avatar
Altera_Forum
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16 years ago

you can setup the spi for 17 bit

shift your data you want to transmit spi_out_data = ( 1,1,0,a6-a0 ) << 8

and when you read data from spi discard to upper 9 bit indata = spi_in_data & 0x0F

this should work in this case as transmit and receive is done at the same time, in your case just imagine that after A0 you send 8 time a 0 and every bit before Dn is not needed

the spi ip also has the capability of extending the transmision. this means after all bits have been transmitted and received, the spi ip does not release CS and keeps it in the active state. if you now start the next transmit & receive, another N clock and shifts will be executed. that is usefull if your protocol needs to transfer longer bit streams.